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I recently started FPGA programming and figured it would be fun to use an FPGA to implement the FizzBuzz algorithm.
An FPGA () is an interesting chip that you can program to implement arbitrary digital logic.
This lets you build a complex digital circuit without wiring up individual gates and flip flops.
It’s like having a custom chip that can be anything from a logic analyzer to a microprocessor to a video generator.
The “” is to write a program that prints the numbers from 1 to 100, except multiples of 3 are replaced with the word “Fizz”, multiples of 5 with “Buzz” and multiples of both with “FizzBuzz”.
Since FizzBuzz can be implemented in a few lines of code, it is used as a programming to weed out people who can’t program at all.
Implementing FizzBuzz in digital logic (as opposed to code) is rather pointless, but I figured it would be a good way to learn FPGAs.1
For this project, I used the FPGA development board (shown above), which was designed to be an easy-to-use starter board.
It uses an FPGA chip from Xilinx’s Spartan 6 family. Although the Mojo’s FPGA is one of the smallest Spartan 6 chips, it still contains over 9000 logic cells and 11,000 flip flops, so it can do a lot.
Implementing serial output on the FPGA
What does it mean to implement FizzBuzz on an FPGA? The general-purpose I/O pins of an FPGA could be connected to anything, so the FizzBuzz output could be displayed in many different ways such as LEDs, seven-segment displays, an LCD panel, or a VGA monitor.
I decided that outputting the text over a serial line to a terminal was the closest in spirit to a “standard” FizzBuzz program.
So the first step was to implement serial output on the FPGA.
The basic idea of serial communication is to send bits over a wire, one at a time.
The
is a simple protocol for serial data, invented in 1960 for connecting things like teletypes and modems.
The diagram below shows how the character “F” (binary 01000110) would be sent serially over the wire.
First, a start bit (low) is sent to indicate the start of a character.2 Next, the 8 bits of the character are sent in reverse order.
Finally, a stop bit (high) is sent to indicate the end of the character.
The line sits idle (high) between characters until another character is ready to send.
For a baud rate of 9600, each bit is sent for 1/9600 of a second. With 8 data bits, no parity bit, and 1 stop bit, the protocol is known as 8N1. Many different serial protocols are in use, but 9600 8N1 is a very common one.
The first step in implementing this serial output was to produce the 1/9600 second intervals for each bit.
This interval can be measured by counting 5208 clock pulses on the Mojo.3
I implemented this by using a 13-bit counter to repeatedly count from 0 to 5207.
To keep track of which bit is being output in each interval, I used a simple state machine that advanced through the start bit, the 8 data bits, and the stop bit.
The state is held in a 4-bit register.
(With FPGAs, you end up dealing a lot with clock pulses, counters, and state machines.)
To create the interval and state registers in the FPGA chip, I wrote code in the Verilog hardware description language.
I won’t explain Verilog thoroughly, but hopefully you can get a feel for how it works.
In the code below,
the first lines define a 13-bit register called counter and a 4-bit register called state. The counter is incremented until it reaches 5207, at which time the counter is reset to 0 and state is incremented to process the next output bit.
(Note that <= is an assignment operator, not a comparison.4)
The line always @(posedge clk) indicates that the code is executed on the positive edge of each clock.
reg [12:0] counter;
reg [3:0] state;
always @(posedge clk) begin
if (counter < 5207) begin
counter
