Die letzten Wochen und Monate waren alles andere als rosig für den Kryptomarkt. Fallende Kurse und schlechte Nachrichten haben stark auf die Stimmung im Krypto-Ökosystem geschlagen – das Schlagwort FUD (Fear, Uncertainty and Doubt) schlug hohe Wellen. In manch einer Berichterstattung konnte schnell der Eindruck gewonnen werden, dass die Krypto-Ökonomie am Ende ist. Wir halten…Der Beitrag erschien zuerst auf .
pre {border:none;background-color:#eee;display:inline-block;min-width:30em;padding:4px;font-size:80%;}
code {background-color:#eee; font-size:100%;}
This blog post shows how you can generate a video signal with an FPGA, using the FizzBuzz problem as an example.
Creating video with an FPGA was easier than I expected, simpler than my previous .
I got a bit carried away with the project and added animation, rainbow text and giant bouncing words to the display.
If you’re not familiar with the ““, the problem is to write a program that prints the numbers from 1 to 100, except multiples of 3 are replaced with the word “Fizz”, multiples of 5 with “Buzz” and multiples of both with “FizzBuzz”.
Since FizzBuzz can be implemented in a few lines of code, it can be used as an to weed out people who can’t program at all.
But it’s much more of a challenge on an FPGA.
An FPGA () is an interesting chip that you can program to implement arbitrary digital logic.
This lets you build a complex digital circuit without wiring up individual gates and flip flops.
It’s like having a custom chip that can be anything from a logic analyzer to a microprocessor to a video generator.
For this project, I used the (below).
Generating the VGA signals
There’s a learning curve to an FPGA, since you’re designing circuits, not writing software that runs on a processor.
But if you can blink five LEDs with an FPGA, you’re most of the way to creating a VGA video signal.
The VGA video format is a lot simpler than I expected:
just
three signals for the pixels (red, green and blue), and
two signals for horizontal sync and vertical sync.
The basic idea is to use two counters: one to count pixels horizontally and one to count lines vertically.
At each spot on the screen, the desired pixel color is generated from these coordinates.
In addition, the horizontal and vertical sync signals are produced when the counters are at the right positions.
I used the basic 640×480 VGA screen resolution2 which requires counting to 800 and 525.111
Horizontally, there are 800 pixels for each line: 640 visible image pixels, followed by 16 blank pixels, 96 pixels of horizontal sync and 48 more blank pixels. (There are historical reasons for these strange numbers.)
Meanwhile, the vertical counter must count out 525 lines: 480 image lines, 10 blank lines, 2 lines of vertical sync and 33 more blank lines.
Putting this all together, I created a vga module () to generate the VGA signals.
This code is in Verilog (a standard language for FPGAs); I won’t explain Verilog thoroughly, but hopefully enough to show how it works.
The code below implements the x and y counters.
The first line indicates action is taken on the positive edge of each (50 MHz) clock signal.
The next line toggles clk25 each clock, creating the 25 MHz signal we’ll use for the pixel clock. (One confusing thing is that <= indicates assignment, not comparison.)
The code increments the x counter from 0 to 799.
At the end of each line, y is incremented, running from 0 to 524.
Thus, this code generates the necessary pixel and line counters.
always @(posedge clk) begin
clk25
